Surrogate-Model-Based Analysis of Analog Circuits-Part I: Variability Analysis


Yelten M. B. , Franzon P. D. , Steer M. B.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol.11, no.3, pp.466-473, 2011 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 11 Issue: 3
  • Publication Date: 2011
  • Doi Number: 10.1109/tdmr.2011.2160062
  • Title of Journal : IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
  • Page Numbers: pp.466-473

Abstract

In this paper, an integrated variability and reliability analysis method based on surrogate models is introduced. The surrogate models here are response surfaces that describe a parametrized complex analytic function. Surrogate models are developed for the drain currents of 65-nm NMOS and PMOS devices in terms of critical process components, terminal voltages, temperature, and time and are based on BSIM model equations. A simulation technique is developed which incorporates the effect of process variations into the design procedure. These models and techniques are verified using circuit simulations of a single transistor and differential amplifier designs.