In this paper, an integrated variability and reliability analysis method based on surrogate models is introduced. The surrogate models here are response surfaces that describe a parametrized complex analytic function. Surrogate models are developed for the drain currents of 65-nm NMOS and PMOS devices in terms of critical process components, terminal voltages, temperature, and time and are based on BSIM model equations. A simulation technique is developed which incorporates the effect of process variations into the design procedure. These models and techniques are verified using circuit simulations of a single transistor and differential amplifier designs.