Multiple-valued static CMOS memory cell


Cilingiroglu U., Ozelci Y.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol.48, no.3, pp.282-290, 2001 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 48 Issue: 3
  • Publication Date: 2001
  • Doi Number: 10.1109/82.924070
  • Journal Name: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Aerospace Database, Applied Science & Technology Source, Communication Abstracts, Compendex, Computer & Applied Sciences, INSPEC, Metadex, Civil Engineering Abstracts
  • Page Numbers: pp.282-290
  • Istanbul Technical University Affiliated: No

Abstract

The conventional flip-flop core is generalized to multistability in full static CMOS without compromising the standard binary CMOS features such as ratioless device sizing, negligible static power consumption, and wide noise margins. The proposed multiple-level cell is built with eight devices for three-level operation and necessitates four more devices for each additional level. It can be arranged with a proper address scheme to function as a RAM cell, D-latch, or synaptic memory. Experimental work verifies four-level operation with 3-V supply. Simulations indicate the possibility of six-level storage in 5-V operation. The cell retains noise margins one threshold voltage wide even at such high-level operation. This is made possible by exploiting the dynamic hysteresis associated with the transfer characteristic of an inverter operating with very low rail-to-rail voltage.