A low-power, low-voltage, single-ended input, four-quadrant CMOS analog multiplier architecture suitable for analog neural network implementations is presented. The architecture takes advantage of the quadratic I-V characteristic of an NMOS and a PMOS transistors both operating in saturation region. Combining NMOS and PMOS transistors allows four-quadrant operation with single-ended input. Due to its modular structure, proposed architecture is very suitable for applications requiring large number of multiplier's in parallel such as neural networks. The cell can operate with a supply voltage level down to 1.2V and draws 2 mu A quiescent current. The circuit is designed and simulated in 0.35 mu m standard CMOS process.