A New Neuron Model Suitable for Low Power VLSI Implementation

Erdener O., Ozoguz S.

9th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Türkiye, 26 - 28 Kasım 2015, ss.15-19 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: Bursa
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.15-19
  • İstanbul Teknik Üniversitesi Adresli: Evet

Özet

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 mu m CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.