A New Neuron Model Suitable for Low Power VLSI Implementation


Erdener O., Ozoguz S.

9th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 26 - 28 November 2015, pp.15-19 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • City: Bursa
  • Country: Turkey
  • Page Numbers: pp.15-19

Abstract

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 mu m CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.