In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 mu m CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.