2011 IEEE 19th Signal Processing and Communications Applications Conference, SIU 2011, Antalya, Turkey, 20 - 22 April 2011, pp.841-844
In this study, a linear single transistor power amplifier with 0.1 - 10 GHz, 0.5W output power at 1dB compression point (P1dB) and >45% power added efficiency (PAE) is designed. By using a graphical load-pull approach to obtain uniform distrubution for both P1dB and PAE, it is showed that the designed amplifier has its advantage over a classical load line mathched amplifier. UMS 900mW/mm 0.25μm GaAs pHEMT technology and ADS design environment is used to fullfill overall design and simulations. © 2011 IEEE.