Power Analysis of an FPGA Implementation of Rijndael Is Pipelining a DPA Countermeasure | AVESİS

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Power Analysis of an FPGA Implementation of Rijndael Is Pipelining a DPA Countermeasure

Standaert F., ÖRS YALÇIN S. B. , Preneel B.

Cryptographic Hardwareand Embedded Systems - CHES, 11 - 13 August 2004, pp.30-44

Publication Type: Conference Paper / Full Text
Doi Number: 10.1007/978-3-540-28632-5_3
Page Numbers: pp.30-44