We examine the differential power analysis attack (DPA) on a pipelined FPGA implementation of AES when decoupling capacitors are in the circuit. In a recent work, researchers pointed out the use of the decoupling capacitors is inevitable for the encryption hardware operating at high clock frequencies. Also, use of the decoupling capacitance is advisable to protect the cryptographic algorithms against DPA attack since current is going to be delivered from the closest capacitor, not from the power supply. In this work we show that decoupling capacitors are not a protection method against DPA attack. In contrast, they are the local source for the charge delivery at high frequencies. Being able to observe the current flow on the pin renders the circuit open for attacks. As a result, integrated circuits (IC) working at high frequency range are still vulnerable to attack. We define the frequencies at which attack is successful. Our work gives the results when we attack on AES implementation by observing decoupling capacitor current flow of an FPGA operating up to 66 MHz clock frequency.