A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications

Ulusoy E., Zencir E.

Journal of Circuits, Systems and Computers, vol.32, no.13, 2023 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 32 Issue: 13
  • Publication Date: 2023
  • Doi Number: 10.1142/s0218126623502237
  • Journal Name: Journal of Circuits, Systems and Computers
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, Applied Science & Technology Source, Computer & Applied Sciences, INSPEC
  • Keywords: Frequency synthesizer, phase locked loop, vehicle to everything, cellular vehicle to everything, loop sampling filter
  • Istanbul Technical University Affiliated: No


In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than-88 dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to-55 dBc. Using the loop sampling technique provides a spur reduction of 33 dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of-97/-99/-114 dBc for 10 kHz/100 kHz/1 MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6 mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18 mW.