This paper describes a new method for the design of wide range adaptive bandwidth PLLs. This method is implemented in two steps. In the first step named as coarse calibration, CCO (current controlled oscillator) center current is found using a digital frequency comparator. Voltage-to-current converters driving the CCO have a constant input voltage range. Additionally, their output current range is proportional to the CCO center current, so VCO gain tracks the center frequency. Charge pump current is also determined based on the update frequency in this step. In the second step named as fine tuning, CCO locks to the target frequency with a phase frequency detector (PFD) around the center current found in the first step. VCO gain tracking and finding the charge pump current based on the update frequency make the natural frequency proportional to the update frequency. Sample-reset loop filter provides a tracking mechanism between the update rate and the stabilizing zero. Furthermore, both the natural frequency and the stabilizing zero are made dependent on the ratio of circuit elements and bandgap reference voltages. This makes the loop dynamics less sensitive to process and temperature variations and virtually independent of output frequency and multiplication factor. The PLL has 500-2500MHz output frequency range and 1 to 50MHz update frequency range. The design was simulated in 0.18 mu m CMOS technology to verify the proposed method.