This paper presents a new digitally-assisted analog foreground comparator offset calibration technique that is fast, compact, low-power, precise, and linear. Non-linear input referred DC offset voltage of a comparator used in an analog-to-digital converter (ADC) is considered as the most important factor that degrades performance, especially for ADC architectures that utilize multiple comparators, such as flash ADCs. This paper discusses the causes of various types of offsets as well as techniques for cancelling them in dynamic latched comparators. Both background and foreground offset calibration techniques used in dynamic comparators are explained. Three popular circuit implementation approaches for foreground calibration are reviewed. A novel coarse-fine calibration (CFC) technique is introduced presenting concept of operation and its effectiveness over other available analog foreground offset calibration techniques. Simulation and measurement results of dynamic comparators that were fabricated in 2P3M, 3.3 V, 0.35 mu m CMOS process are presented. It was shown that the proposed CFC technique achieves better performance than other digitally-assisted analog calibration techniques without requiring high-resolution (> 8-bit) trimming digital-to-analog converters while providing compact, high-speed, low-power, and linear offset correction over the full offset range of up to +/- 100 mV.