Dead-Time Analysis in Three-Phase Two-Level Inverters using the SVPWM Technique


Akgül K., Ergenç A. F., Yılmaz M., Ergene L.

4th IEEE Global Power, Energy and Communication Conference (IEEE GPECOM), Cappadocia, Turkey, 14 - 17 June 2022, pp.210-215 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/gpecom55404.2022.9815623
  • City: Cappadocia
  • Country: Turkey
  • Page Numbers: pp.210-215
  • Keywords: Compensation, Dead-time, Three-Phase Inverter, SVPWM, Variable Speed Drive, Total Harmonic Distortion
  • Istanbul Technical University Affiliated: Yes

Abstract

Inverters have many application areas including the variable frequency drives applications of the motor industry. Three-phase inverters based on the three-phase system that we are using are becoming more common. The implementation of the space vector PWM (SVPWM) modulation technique in three-phase inverters is more advantageous than other modulation techniques due to the lower harmonic content and higher DC bus utilization it provides. A delay time, also called the dead-time, is added to the rising edge of the PWM signals for triggering the gates of the switches to avoid shoot-through faults in the inverters. Although it has a protection advantage, it has some disadvantages such as output voltage drop, phase shift, zero current clamping and increase in total harmonic distortion (THD) of the output current. In this study, these effects of dead-time are compensated by employing the simple yet effective feedforward method using the SVPWM technique. Moreover, the relationship between the effects of the dead-time and switching frequency is investigated. The results exhibit that the THD of the current is optimized when the switching frequency is controlled rather than kept constant.