Fully CMOS Memristor Based Chaotic Circuit


Yener S. C. , Kuntman H. H.

RADIOENGINEERING, vol.23, no.4, pp.1140-1149, 2014 (Journal Indexed in SCI) identifier

  • Publication Type: Article / Article
  • Volume: 23 Issue: 4
  • Publication Date: 2014
  • Title of Journal : RADIOENGINEERING
  • Page Numbers: pp.1140-1149

Abstract

This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 mu m process technology with symmetric +/- 1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.