In this paper we present simulation and measurements for output offset in integrated silicon Hall sensors. Using FEM simulations of various sensor structures, sources of output offset and methods to mitigate this are identified. The simulation results indicate that using cross-shaped sensors exhibit 75% higher variance than octagon shaped sensors as well as sensors shaped as a square with rounded corners. It is determined that restricting the direct current flow path would yield larger offset variances. Additionally the measurements indicate that there are proximity effects that also impact the offset in addition to the geometry. Sensors surrounded by other structures do exhibit the variation relations observed in the simulations. The sensors located on the edges exhibit additional sensor offset variation. The measured sensor offsets vary between 5 mV-20 mV including proximity effects. If we can reduce proximity effects the variation is measured from 5 mV to 10 mV. Therefore reducing the Hall sensor output voltage offset variance involves using dummy devices as avoidance of restrictions on the current flow. (C) 2019 Elsevier B.V. All rights reserved.