The functional yield is becoming increasingly critical in VLSI design. As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analog integrated circuits is magnified. The statistical MOS (SMOS) model accounts for both inter-die and intradie variations. A new transconductor, statistically robust with good yield is discussed in this paper. The circuit operates in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response Surface Methodology and Design of Experiment techniques were used as statistical VLSI design tools combined with the SMOS model. Device size optimization and yield enhancement have been demonstrated.