Design and Implementation of TLS Accelerator

Yildiz R. O., Yılmazer Metin A.

15th IEEE Dallas Circuit and System Conference (DCAS), Texas, United States Of America, 17 - 19 June 2022 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/dcas53974.2022.9845527
  • City: Texas
  • Country: United States Of America
  • Keywords: TLS, accelerator, FPGA
  • Istanbul Technical University Affiliated: Yes


Communication devices deploy messages to another one over either a controlled channel or a non-controlled channel. When the communication channel is non-controlled, the deployed message is available for anyone that is able to listen. But, the deployed message may comprise private information that needs to be shared securely. Therefore, to establish a secure communication over a controlled or a non-controlled channel, cryptography algorithms are used. The Transport Layer Security (TLS) is a protocol that includes several cryptography algorithms. With its algorithms, TLS provides authentication, confidentiality, and data integrity features. These features achieved with repeated calculations. Yet, these calculations increase the power consumption and degrade the performance of a sequential processor. To overcome these problems, an accelerator can be used for the calculations of TLS protocol. In this work, a TLS accelerator is designed and implemented on an FPGA. Our design aims to increase the performance and decrease the power consumption of sequential processor during the TLS calculations. The proposed accelerator is implemented with Xilinx Vivado and the implementation results show that the proposed accelerator consumes 0.86 Watt power. The accelerator is simulated with Vivado in order to measure the throughput of the proposed accelerator. The encryption throughput of the proposed accelerator at 100 MHz operating frequency is observed as 700 Mbps. Also, the proposed accelerator provides 52.4 handshake connections per second.