A 50V Input Range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR


Ozkaya I., Gurleyuk C., Ergul A., Akkaya A., Aksin D. Y.

40th European Solid-State Circuit Conference (ESSCIRC), Venezia Lido, Italy, 22 - 26 September 2014, pp.71-74 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Venezia Lido
  • Country: Italy
  • Page Numbers: pp.71-74

Abstract

A 50V input range, common-mode and differential, 14bit 2-step SAR ADC is presented. The ADC operating at 250kS/s for a 50V(PP) input signal on a 15V common-mode voltage achieves 97.8dB SFDR and 80.2dB SNR, while consuming 4.29mW from a single 33V supply. The 2-step architecture accomplishes an increase in resolution by reusing conversion residue, with a time-shared configurable amplifier/comparator block and SAR hardware. The high SFDR figure achieved without trimming, calibration or tuning asserts the linearity of the implemented high-voltage bootstrapped switch and the capacitive DAC array. The ADC provides an alternative, lower-power solution to high voltage data acquisition, by removing the need for off chip or silicon expensive components.