High-Performance Multi-Pattern Matching Structure in Hardware Network Firewall


Wang Jie W. J. , Ji Zhen-zhou J. Z. , Hu Ming-zeng H. M.

9th WSEAS International Conference on Applied Informatics and Communications, Moscow, Russia, 20 - 22 August 2009, pp.187-188 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Moscow
  • Country: Russia
  • Page Numbers: pp.187-188

Abstract

Along with development of network techniques and firewall techniques, multi-pattern matching for content filtering, virus detection and other network security measures is emphasized in the field of hardware firewall. Principles of multi-pattern matching on network firewall based on FPGA (Field Programmable Gate Array) are presented: low latency, supporting non-fixed-length pattern and forward matching. And architecture of high-performance matching on data link layer forming pipeline with frame transmission is proposed especially for multi-port scheduling. By academic analysis and experimental validation it can support applications of high-performance hardware network firewall and effectively reduce additional delays by expand logics.