Multiplier-less 1-Level Discrete Wavelet Transform Implementations on ZC706 development kit

Alzaq H., Üstündağ B. B.

10th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 30 November - 02 December 2017, pp.1122-1126 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Bursa
  • Country: Turkey
  • Page Numbers: pp.1122-1126
  • Istanbul Technical University Affiliated: Yes


In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx ZYNQ-7000 FPGA, taking advantage of embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.