Synthesis and Fundamental Energy Analysis of Fault-Tolerant CMOS Circuits

ERCAN İ., Susam O., Altun M. , Cilasun M. H.

13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) / 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Application to Circuit Design (SMACD), Italy, 12 - 15 June 2017 identifier

  • Publication Type: Conference Paper / Full Text
  • Country: Italy


In this study, we perform a physical-information-theoretic analysis to obtain fundamental energy dissipation bounds for fault-tolerant reversible CMOS circuits we synthesize using Hamming codes. We show that the approach we had initially developed to calculate theoretical efficiency limitations of emerging electronic paradigms can also be applied to CMOS technology base and can provide feedback to improve circuit design and performance. We illustrate our physical-information-theoretic methodology via applications to circuits that we synthesized using Hamming codes that result in detection of up to (d-1) bit errors and correction of up to (d-1)/2 bit errors where d represents the minimum Hamming distance between any pair of bit patterns. The fundamental lower bounds on energy dissipation are calculated for a one-bit reversible full adder and for irreversible full adders with block-code-, dual modular redundancy (DMR)- and triple modular redundancy (TMR)-based CMOS circuits. Our results reflect the fundamental difference in energy limitations across these circuits and provide insights into improved design strategies.