Power-analysis attack on an ASIC AES implementation


Ors S. B. , GURKAYNAK F. K. , OSWALD E., PRENEEL B.

International Conference on Information Technology - Coding and Computing, Nevada, United States Of America, 5 - 07 April 2004, pp.546-552 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/itcc.2004.1286711
  • City: Nevada
  • Country: United States Of America
  • Page Numbers: pp.546-552

Abstract

The AES (Advanced Encryption Standard) is a new block cipher standard published by the US government in November 2001. As a consequence, there is a growing interest in efficient implementations of the AES. For many applications, these implementations need to be resistant against side channel attacks, that is, it should not be too easy to extract secret information from physical measurements on the device. This article presents the first results on the feasibility of power analysis attack against an AES hardware implementation. Our attack is targeted against an ASIC implementation of the AES developed by the ETH Zurich. We show how to build a reliable measurement setup and how to improve the correlation coefficients, i.e., the signal to noise ratio for our measurements. Our approach is also the first step to link a behavior HDL simulator generated simulated power measurements to real power measurements.