Emulating CNN with Template Learning on FPGA


Kose E., Yalcin M. E.

European Conference on Circuit Theory and Design (ECCTD), Catania, Italy, 4 - 06 September 2017 identifier identifier

Abstract

A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is shown. SoC design is programmed to perform a sequential CNN operations on different input and state images with different templates. Furthermore, the presented SoC design allows that templates can be updated by a learning algoritm in run time. SoC design is realised on a target FPGA. Test results on FPGA and MATLAB are presented and compared with structural similarity map.