Analog and Short Channel Effects Performance of Sub-100 nm Graded Channel Fully Depleted Silicon On Insulator (SOI)

Jafar N., Soin N.

8th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics, İstanbul, Turkey, 30 May - 01 June 2009, pp.63-67 identifier

  • Publication Type: Conference Paper / Full Text
  • City: İstanbul
  • Country: Turkey
  • Page Numbers: pp.63-67
  • Istanbul Technical University Affiliated: No


This paper presents the dependency of analog and Short Channel Effects (SCEs) performance of 75 nm channel length fully-depleted Silicon On Insulator (SOI) device on the applied Graded Channel (GC) design. The comparative analysis between standard SOI (STD SOI) devices at doped channel and equivalent threshold voltage, V(TH) with GC SOI device are examined on the basis of internal physical mechanisms. Device characterizations are performed using simulation based approached provided by ATLAS 2D. Results show superiority of GC performances over standard SOI devices in both analog and SCEs point of views.