Optimization of area in digital FIR filters using gate-level metrics

Aksoy L., Costa E., Flores P., Monteiro J.

44th ACM/IEEE Design Automation Conference, California, United States Of America, 4 - 08 June 2007, pp.420-421 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/dac.2007.375200
  • City: California
  • Country: United States Of America
  • Page Numbers: pp.420-421
  • Istanbul Technical University Affiliated: Yes


In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR filters. Previous methods use the number of required additions or subtractions as a cost function. We make the observation that not all of these operations have the same design cost. In the proposed algorithm, a minimum area solution is obtained by considering area estimates for each operation. To this end, we introduce accurate hardware models for addition-and subtraction operations in terms of gate-level metrics. under both signed and unsigned representations. Our algorithm not only computes the best design solution among those that have the same number of operations, but is also able to find better area solutions using a non-minimum number of operations. The results obtained by the proposed exact algorithm are compared with the results of the exact algorithm designed for the minimum number of operations on FIR filters and it is shown that the area of the design can be reduced by up to 18%.