A 12-bit 0.35 mu m CMOS area optimized current-steering hybrid DAC


ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol.65, no.1, pp.67-75, 2010 (SCI-Expanded) identifier identifier


In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 mu m CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.