Implementation of a SoC by Using lowRISC Architecture on an FPGA for Image Filtering Applications Görüntü Filtreleme Uygulamalari için lowRISC Mimarisini Kullanan Kirmik Üstü Sistem Tasarimi ve FPGA Üzerinde Gerçeklenmesi

Akcay L., Surer B., Yalcin B. O.

30th Signal Processing and Communications Applications Conference, SIU 2022, Safranbolu, Turkey, 15 - 18 May 2022 identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/siu55565.2022.9864960
  • City: Safranbolu
  • Country: Turkey
  • Keywords: image processing, lane detection, lowRISC, RISC-V, system on chip
  • Istanbul Technical University Affiliated: Yes


© 2022 IEEE.In this study, it is aimed to implement the low-RISC system-on-chip, which is based on the Rocket processor created with the RISC-V instruction set architecture developed by Berkeley University, on FPGA and to run image processing algorithms on this system. While making this implementation, the main target is a system that is very simple, consumes low power, and can be quickly redirected to other purposes. Therefore, it is based on the effective evaluation of the existing system without using any extra customized accelerators. Thus, a free, open source, and powerful enough platform for many embedded system applications is proposed to the designers. For this purpose, a lane detection application designed with standard C libraries such as Gaussian blur filter, Sobel operation filter and other elements, which are widely used in image processing applications, is run with embedded Linux operating system and the results are shared.