This paper describes a novel sub-threshold voltage reference generator suitable for very low power and very low voltage wearable systems. Indeed, the circuit, designed and extensively simulated in a standard 0.18-mu m CMOS technology, generates a 51.3-mV output voltage with a nominal supply voltage of 0.5 V and consumes as low as 185 nW. Design optimisation and a first order temperature compensation allow achieving a temperature coefficient of 25.4 ppm/degrees C in the temperature range from -40 to 125 degrees C. The proposed architecture optimizes the output noise performance by minimizing the current mirrors flicker and thermal noise contributions which, in conventional schemes, severely affect the output node. In addition, the same circuital arrangement allows obtaining high power supply rejection (PSR). The simulated root mean square output noise is 1.6 mu V in the frequency range from 0.1 Hz to 10 Hz, while the PSR is -76 dB at 100 Hz, a remarkable value.