This paper presents surrogate model-based methods to generate circuit performance models, device models, and high-speed ID buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. A new variation-aware IO buffer macromodel is developed by integrating surrogate modeling and a physically-based model structure. The new IO model provides both good accuracy and scalability for signal integrity analysis.