TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology


Kizil H. , Kım G., Steınbruchel C., Zhao B.

JOURNAL OF ELECTRONIC MATERIALS, vol.30, pp.345-348, 2001 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 30
  • Publication Date: 2001
  • Doi Number: 10.1007/s11664-001-0041-z
  • Title of Journal : JOURNAL OF ELECTRONIC MATERIALS
  • Page Numbers: pp.345-348

Abstract

The present status of work on diffusion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TIN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.