Comparison of modeling techniques in circuit variability analysis


Yelten M. B., Franzon P. D., Steer M. B.

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, vol.25, no.3, pp.288-302, 2012 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 25 Issue: 3
  • Publication Date: 2012
  • Doi Number: 10.1002/jnm.836
  • Journal Name: INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.288-302
  • Keywords: artificial neural network, digital circuit, drain current, Kriging, least-squares support vector machine, surrogate modeling, variability Analysis, XOR, ANALOG CIRCUITS, DESIGNS, DEVICES
  • Istanbul Technical University Affiliated: No

Abstract

Three nonlinear reduced-order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal-oxide-semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65?nm N-type metal-oxide-semiconductor and P-type metal-oxide-semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging-based surrogate models, neural network-based models, and support vector machine-based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging-based surrogate models and neural network-based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging-based surrogate modeling yields results faster than the neural network-based models for the same accuracy whereas for larger circuits, neural network-based models are preferred as, in all metrics, better performance is obtained. Within-die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced-order models developed can more effectively capture the within-die variations than the traditional process corner analysis. Copyright (C) 2011 John Wiley & Sons, Ltd.