Efficient architectures for time-interleaved oversampling delta-sigma converters


Kozak M., Karaman M. , Kale I.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, vol.47, no.8, pp.802-810, 2000 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 47 Issue: 8
  • Publication Date: 2000
  • Doi Number: 10.1109/82.861422
  • Title of Journal : IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
  • Page Numbers: pp.802-810

Abstract

A design methodology utilizing the concept of time-interleaved oversampling delta-sigma conversion is developed and explored to obtain efficient hardware architectures. In this approach, the time-domain internal node expressions of a standard modulator are rearranged according to the desired channel count to produce a modular structure with reduced hardware requirements. It is shown that the proposed approach results in an architecture which is functionally equivalent to that of the conventional method based on the block-digital filtering concept, brit with a reduced hardware complexity. The theoretical results are also verified by means of behavioral simulations.